WhyCan Forum(哇酷开发者社区)

&pio {
	aw9523b_pins: aw9523b-pins {
		pins = "PE10";
		function = "gpio_in";
		bias-pull-up;
	};
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pe_pins>;
	status = "okay";

	aw9523b: gpio-expander@5b {
		compatible = "awinic,aw9523b-gpio";
		reg = <0x5b>;
		pinctrl-names = "default";
		pinctrl-0 = <&aw9523b_pins>;
		interrupt-parent = <&pio>;
		interrupts = <4 10 IRQ_TYPE_EDGE_FALLING>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		wakeup-source;
	};
};

    cd configs
    ln -s ../board/widora/tiny200/widora_tiny200_defconfig .
    make widora_tiny200_defconfig

sunxi-fel -p uboot output/images/u-boot-sunxi-with-spl.bin
fastboot oem format
fastboot flash loader output/images/u-boot-sunxi-with-spl.bin
fastboot flash esp output/images/boot.vfat
fastboot flash system output/images/rootfs.ext4
fastboot reboot

diff --git a/Kconfig b/Kconfig
index 8bae87e3f6..cc625d0253 100644
--- a/Kconfig
+++ b/Kconfig
@@ -589,9 +589,9 @@ config HAVE_SYS_TEXT_BASE
 config SYS_TEXT_BASE
 	depends on HAVE_SYS_TEXT_BASE
 	default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3
-	default 0x4a000000 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S
+	default 0x4a000000 if ARCH_SUNXI && !MACH_SUN9I && (!MACH_SUN8I_V3S || !MACH_SUN8I_S3)
 	default 0x2a000000 if ARCH_SUNXI && MACH_SUN9I
-	default 0x42e00000 if ARCH_SUNXI && MACH_SUN8I_V3S
+	default 0x42e00000 if ARCH_SUNXI && (MACH_SUN8I_V3S || MACH_SUN8I_S3)
 	hex "Text Base"
 	help
 	  The address in memory that U-Boot will be running from, initially.
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bb979550c4..bbe1887623 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -546,7 +546,9 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
 	sun8i-r40-bananapi-m2-ultra.dtb \
 	sun8i-v40-bananapi-m2-berry.dtb
 dtb-$(CONFIG_MACH_SUN8I_V3S) += \
-	sun8i-v3s-licheepi-zero.dtb
+	sun8i-v3s-licheepi-zero.dtb 
+dtb-$(CONFIG_MACH_SUN8I_S3) += \
+	sun8i-s3-generic.dtb
 dtb-$(CONFIG_MACH_SUN50I_H5) += \
 	sun50i-h5-bananapi-m2-plus.dtb \
 	sun50i-h5-emlid-neutis-n5-devboard.dtb \
diff --git a/arch/arm/dts/sun8i-s3-generic.dts b/arch/arm/dts/sun8i-s3-generic.dts
new file mode 100644
index 0000000000..c1aac3d5d4
--- /dev/null
+++ b/arch/arm/dts/sun8i-s3-generic.dts
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2020 Aodzip <aodzip@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-s3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+    model = "Allwinner S3 Generic Device";
+    compatible = "allwinner,sun8i-s3";
+
+    aliases {
+        serial0 = &uart0;
+    };
+
+    chosen {
+        stdout-path = "serial0:115200n8";
+    };
+
+    backlight: backlight {
+        compatible = "pwm-backlight";
+        pwms = <&pwm 0 50000 0>;
+        brightness-levels = <0 2 4 8 16 32 64 128 255>;
+        default-brightness-level = <8>;
+    };
+
+    panel-rgb@0 {
+        compatible = "simple-panel";
+        backlight = <&backlight>;
+
+        display-timings {
+            timing@0 {
+                clock-frequency = <50000000>;
+                hactive = <480>;
+                vactive = <272>;
+                hfront-porch = <2>;
+                hback-porch = <2>;
+                hsync-len = <41>;
+                vfront-porch = <2>;
+                vback-porch = <2>;
+                vsync-len = <10>;
+                hsync-active = <0>;
+                vsync-active = <0>;
+                de-active = <0>;
+                pixelclk-active = <1>;
+            };
+        };
+    };
+};
+
+&emac {
+    phy-handle = <&int_mii_phy>;
+    phy-mode = "mii";
+    allwinner,use-internal-phy;
+    status = "okay";
+};
+
+&mmc0 {
+    bus-width = <4>;
+    status = "okay";
+};
+
+&mmc2 {
+    non-removable;
+    max-speed = <20000000>;
+    bus-width = <8>;
+    status = "okay";
+};
+
+&spi0 {
+    status = "disabled";
+};
+
+&uart0 {
+    status = "okay";
+};
+
+&usb_otg {
+    status = "okay";
+};
+
+&usbphy {
+    status = "okay";
+};
+
+&ehci0 {
+    status = "okay";
+};
+
+&ohci0 {
+    status = "okay";
+};
+
+&pwm {
+    status = "okay";
+};
diff --git a/arch/arm/dts/sun8i-s3.dtsi b/arch/arm/dts/sun8i-s3.dtsi
new file mode 100644
index 0000000000..282aadff11
--- /dev/null
+++ b/arch/arm/dts/sun8i-s3.dtsi
@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) 2020 Aodzip <aodzip@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "sun8i-v3s.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+    #address-cells = <1>;
+    #size-cells = <1>;
+    interrupt-parent = <&gic>;
+    
+    soc {
+        compatible = "simple-bus";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+
+        syscon: syscon@1c00000 {
+            compatible = "allwinner,sun8i-v3s-system-controller", "allwinner,sun8i-h3-system-control", "syscon";
+            reg = <0x01c00000 0x1000>;
+        };
+
+        emac: ethernet@1c30000 {
+            compatible = "allwinner,sun8i-h3-emac";
+            syscon = <&syscon>;
+            reg = <0x01c30000 0x10000>;
+            interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+            interrupt-names = "macirq";
+            resets = <&ccu RST_BUS_EMAC>;
+            reset-names = "stmmaceth";
+            clocks = <&ccu CLK_BUS_EMAC>;
+            clock-names = "stmmaceth";
+            status = "disabled";
+
+            mdio: mdio {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "snps,dwmac-mdio";
+            };
+
+            mdio-mux {
+                compatible = "allwinner,sun8i-h3-mdio-mux";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                mdio-parent-bus = <&mdio>;
+                /* Only one MDIO is usable at the time */
+                internal_mdio: mdio@1 {
+                    compatible = "allwinner,sun8i-h3-mdio-internal";
+                    reg = <1>;
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+
+                    int_mii_phy: ethernet-phy@1 {
+                        compatible = "ethernet-phy-ieee802.3-c22";
+                        reg = <1>;
+                        clocks = <&ccu CLK_BUS_EPHY>;
+                        resets = <&ccu RST_BUS_EPHY>;
+                    };
+                };
+
+                external_mdio: mdio@2 {
+                    reg = <2>;
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+                };
+            };
+        };
+
+        ehci0: usb@01c1a000 {
+            compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci";
+            reg = <0x01c1a000 0x100>;
+            interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
+            resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+            status = "disabled";
+        };
+
+        ohci0: usb@01c1a400 {
+            compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci";
+            reg = <0x01c1a400 0x100>;
+            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
+            resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+            status = "disabled";
+        };
+
+        spi0: spi@1c68000 {
+            compatible = "allwinner,sun8i-h3-spi";
+            reg = <0x01c68000 0x1000>;
+            interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+            clock-names = "ahb", "mod";
+            resets = <&ccu RST_BUS_SPI0>;
+            status = "disabled";
+            #address-cells = <1>;
+            #size-cells = <0>;
+        };
+
+        pwm: pwm@1c21400 {
+            compatible = "allwinner,sun5i-a13-pwm";
+            reg = <0x01c21400 0x8>;
+            clocks = <&osc24M>;
+            #pwm-cells = <3>;
+            status = "disabled";
+        };
+    };
+};
+
+&usb_otg {
+    phys = <&usbphy>;
+    extcon = <&usbphy>;
+};
+
+&usbphy {
+    #phy-cells = <0>;
+};
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index ee387127f3..8001a81b8f 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -333,9 +333,14 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_LCD1		5
 #define AHB_GATE_OFFSET_LCD0		4
 #else
+#if defined(CONFIG_MACH_SUN8I_V3S) || defined(CONFIG_MACH_SUN8I_S3)
+#define AHB_GATE_OFFSET_LCD1		5
+#define AHB_GATE_OFFSET_LCD0		4
+#else
 #define AHB_GATE_OFFSET_LCD1		4
 #define AHB_GATE_OFFSET_LCD0		3
 #endif
+#endif
 
 #define CCM_NAND_CTRL_M(x)		((x) - 1)
 #define CCM_NAND_CTRL_N(x)		((x) << 16)
@@ -480,9 +485,14 @@ struct sunxi_ccm_reg {
 #define AHB_RESET_OFFSET_LCD1		5
 #define AHB_RESET_OFFSET_LCD0		4
 #else
+#if defined(CONFIG_MACH_SUN8I_V3S) || defined(CONFIG_MACH_SUN8I_S3)
+#define AHB_RESET_OFFSET_LCD1		5
+#define AHB_RESET_OFFSET_LCD0		4
+#else
 #define AHB_RESET_OFFSET_LCD1		4
 #define AHB_RESET_OFFSET_LCD0		3
 #endif
+#endif
 
 /* ahb_reset2 offsets */
 #define AHB_RESET_OFFSET_EPHY		2
@@ -508,7 +518,12 @@ struct sunxi_ccm_reg {
 /* CCM bits common to all Display Engine 2.0 clock ctrl regs */
 #define CCM_DE2_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
 #define CCM_DE2_CTRL_PLL_MASK		(3 << 24)
+
+#if defined(CONFIG_MACH_SUN8I_V3S) || defined(CONFIG_MACH_SUN8I_S3)
+#define CCM_DE2_CTRL_PLL6_2X		(2 << 24)
+#else
 #define CCM_DE2_CTRL_PLL6_2X		(0 << 24)
+#endif
 #define CCM_DE2_CTRL_PLL10		(1 << 24)
 #define CCM_DE2_CTRL_GATE		(0x1 << 31)
 
diff --git a/arch/arm/include/asm/arch-sunxi/display2.h b/arch/arm/include/asm/arch-sunxi/display2.h
index 7202d2756c..ad3a81dbde 100644
--- a/arch/arm/include/asm/arch-sunxi/display2.h
+++ b/arch/arm/include/asm/arch-sunxi/display2.h
@@ -137,4 +137,12 @@ struct de_csc {
 
 #define SUNXI_DE2_WH(w, h)			(((h - 1) << 16) | (w - 1))
 
+#if defined(CONFIG_MACH_SUN8I_V3S) || defined(CONFIG_MACH_SUN8I_S3)
+	#define SUNXI_DE2_MUX_CHAN_SZ_COUNT 2
+	#define SUNXI_DE2_BLD_ROUTE 2
+#else
+	#define SUNXI_DE2_MUX_CHAN_SZ_COUNT 1
+	#define SUNXI_DE2_BLD_ROUTE 1
+#endif
+
 #endif /* _SUNXI_DISPLAY2_H */
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index be0822bfb7..b7cb87a98f 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -262,7 +262,18 @@ config MACH_SUN8I_V3S
 	select SUNXI_DRAM_DW
 	select SUNXI_DRAM_DW_16BIT
 	select SUPPORT_SPL
-	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+
+config MACH_SUN8I_S3
+	bool "sun8i (Allwinner S3)"
+	select CPU_V7A
+	select CPU_V7_HAS_NONSEC
+	select CPU_V7_HAS_VIRT
+	select ARCH_SUPPORT_PSCI
+	select SUNXI_GEN_SUN6I
+	select SUNXI_DRAM_DW
+	select SUNXI_DRAM_DW_16BIT
+	select SUPPORT_SPL
+	select SUNXI_DE2
 
 config MACH_SUN9I
 	bool "sun9i (Allwinner A80)"
@@ -321,6 +332,7 @@ config MACH_SUN8I
 	default y if MACH_SUNXI_H3_H5
 	default y if MACH_SUN8I_R40
 	default y if MACH_SUN8I_V3S
+	default y if MACH_SUN8I_S3
 
 config RESERVE_ALLWINNER_BOOT0_HEADER
 	bool "reserve space for Allwinner boot0 header"
@@ -437,7 +449,7 @@ config DRAM_ZQ
 	default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
 		       MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
 	default 127 if MACH_SUN7I
-	default 14779 if MACH_SUN8I_V3S
+	default 14779 if MACH_SUN8I_V3S || MACH_SUN8I_S3
 	default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
 	default 4145117 if MACH_SUN9I
 	default 3881915 if MACH_SUN50I
@@ -755,6 +767,7 @@ config VIDEO_SUNXI
 	depends on !MACH_SUNXI_H3_H5
 	depends on !MACH_SUN8I_R40
 	depends on !MACH_SUN8I_V3S
+	depends on !MACH_SUN8I_S3
 	depends on !MACH_SUN9I
 	depends on !MACH_SUN50I
 	depends on !MACH_SUN50I_H6
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index b487b265af..6aa28bbc3c 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -117,7 +117,7 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
+#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN8I_V3S) || defined(CONFIG_MACH_SUN8I_S3))
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
index ae4745bfec..060fbfc8a9 100644
--- a/arch/arm/mach-sunxi/cpu_info.c
+++ b/arch/arm/mach-sunxi/cpu_info.c
@@ -90,6 +90,8 @@ int print_cpuinfo(void)
 	printf("CPU:   Allwinner R40 (SUN8I %04x)\n", sunxi_get_sram_id());
 #elif defined CONFIG_MACH_SUN8I_V3S
 	printf("CPU:   Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
+#elif defined CONFIG_MACH_SUN8I_S3
+	printf("CPU:   Allwinner S3 (SUN8I %04x)\n", sunxi_get_sram_id());
 #elif defined CONFIG_MACH_SUN9I
 	puts("CPU:   Allwinner A80 (SUN9I)\n");
 #elif defined CONFIG_MACH_SUN50I
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index 85e7a1874e..43db624d8b 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -727,6 +727,9 @@ unsigned long sunxi_dram_init(void)
 #elif defined(CONFIG_MACH_SUN8I_V3S)
 	/* TODO: set delays and mbus priority for V3s */
 	uint16_t socid = SOCID_H3;
+#elif defined(CONFIG_MACH_SUN8I_S3)
+	/* TODO: set delays and mbus priority for S3 */
+	uint16_t socid = SOCID_H3;
 #elif defined(CONFIG_MACH_SUN50I)
 	uint16_t socid = SOCID_A64;
 #elif defined(CONFIG_MACH_SUN50I_H5)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 6afea6ef42..769530412b 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -40,6 +40,7 @@
 #include <spl.h>
 #include <sy8106a.h>
 #include <asm/setup.h>
+#include <splash.h>
 
 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
@@ -501,6 +502,13 @@ static void mmc_pinmux_setup(int sdc)
 		sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
 		sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
+#ifdef CONFIG_MACH_SUN8I_S3
+		for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(10); pin++) {
+			sunxi_gpio_set_cfgpin(pin, 2);
+			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(pin, 2);
+		}
+#else
 		/* SDC2: PC5-PC6, PC8-PC16 */
 		for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
 			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
@@ -513,6 +521,7 @@ static void mmc_pinmux_setup(int sdc)
 			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(pin, 2);
 		}
+#endif
 #elif defined(CONFIG_MACH_SUN50I_H6)
 		/* SDC2: PC4-PC14 */
 		for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
@@ -916,3 +925,41 @@ int board_fit_config_name_match(const char *name)
 	return strcmp(name, cmp_str);
 }
 #endif
+
+#ifdef CONFIG_SPLASH_SCREEN
+static struct splash_location sunxi_splash_locations[] = {
+	{
+		.name = "mmc0_fs",
+		.storage = SPLASH_STORAGE_MMC,
+		.flags = SPLASH_STORAGE_FS,
+		.devpart = "0:1",
+	},
+	{
+		.name = "mmc1_fs",
+		.storage = SPLASH_STORAGE_MMC,
+		.flags = SPLASH_STORAGE_FS,
+		.devpart = "1:1",
+	},
+};
+
+int splash_screen_prepare(void)
+{
+	return splash_source_load(sunxi_splash_locations,
+				  ARRAY_SIZE(sunxi_splash_locations));
+}
+
+int initr_env_dynamic_default(void)
+{
+	uint boot = sunxi_get_boot_device();
+	switch (boot) {
+		case BOOT_DEVICE_MMC1:
+			env_set("splashsource", "mmc0_fs");
+			break;
+		case BOOT_DEVICE_MMC2:
+			env_set("splashsource", "mmc1_fs");
+			break;
+	}
+	return 0;
+}
+
+#endif
diff --git a/common/board_r.c b/common/board_r.c
index 0bbeaa7594..949169895d 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -777,6 +777,9 @@ static init_fnc_t init_sequence_r[] = {
 	initr_mmc,
 #endif
 	initr_env,
+#ifdef CONFIG_ENV_DYNAMIC_DEFAULT
+	initr_env_dynamic_default,
+#endif
 #ifdef CONFIG_SYS_BOOTPARAMS_LEN
 	initr_malloc_bootparams,
 #endif
diff --git a/configs/allwinner_s3_generic_defconfig b/configs/allwinner_s3_generic_defconfig
new file mode 100644
index 0000000000..2c368215ed
--- /dev/null
+++ b/configs/allwinner_s3_generic_defconfig
@@ -0,0 +1,54 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_S3=y
+
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-generic"
+CONFIG_SPL=y
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_BOOTDELAY=0
+
+CONFIG_NETDEVICES=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+
+CONFIG_DM_SPI=y
+CONFIG_SUNXI_SPI=y
+
+CONFIG_MMC=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_MMC0_CD_PIN="PF6"
+
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BPP8=y
+CONFIG_VIDEO_SIMPLE=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+
+CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_SUNXI=y
+CONFIG_BACKLIGHT_PWM=y
+
+CONFIG_USB_GADGET_VBUS_DRAW=250
+
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT=y
+CONFIG_USB_MUSB_PIO_ONLY=y
+CONFIG_USB_STORAGE=y
+
+CONFIG_PHY=y
+CONFIG_PHY_SUN4I_USB=y
+
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+
+CONFIG_CMD_USB_MASS_STORAGE=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH_MMC=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index 5ff101b993..c48717bbbc 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -52,11 +52,11 @@ config CLK_SUN8I_R40
 	  on Allwinner R40 SoC.
 
 config CLK_SUN8I_V3S
-	bool "Clock driver for Allwinner V3S"
-	default MACH_SUN8I_V3S
+	bool "Clock driver for Allwinner V3S/S3"
+	default MACH_SUN8I_V3S || MACH_SUN8I_S3
 	help
 	  This enables common clock driver support for platforms based
-	  on Allwinner V3S SoC.
+	  on Allwinner V3S/S3 SoC.
 
 config CLK_SUN9I_A80
 	bool "Clock driver for Allwinner A80"
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index 789ac72026..2101efd11f 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -16,16 +16,22 @@ static struct ccu_clk_gate v3s_gates[] = {
 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_BUS_EMAC]		= GATE(0x060, BIT(17)),
 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
+	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(26)),
+	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(29)),
 
 	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
 	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
 	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
 
+	[CLK_BUS_EPHY]		= GATE(0x070, BIT(0)),
+
 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
 
-	[CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
+	[CLK_USB_PHY0] 		= GATE(0x0cc, BIT(8)),
+	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
 };
 
 static struct ccu_reset v3s_resets[] = {
@@ -34,8 +40,13 @@ static struct ccu_reset v3s_resets[] = {
 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
+	[RST_BUS_EMAC]		= RESET(0x2c0, BIT(17)),
 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
+	[RST_BUS_EHCI0]		= RESET(0x2c0, BIT(26)),
+	[RST_BUS_OHCI0]		= RESET(0x2c0, BIT(29)),
+
+	[RST_BUS_EPHY]		= RESET(0x2c8, BIT(2)),
 
 	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
 	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 9f426661c4..20a622dd2e 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -628,7 +628,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
 	cfg->f_min = 400000;
-	cfg->f_max = 52000000;
+	cfg->f_max = dev_read_u32_default(dev, "max-speed", 52000000);
 
 	priv->reg = (void *)dev_read_addr(dev);
 	priv->variant =
diff --git a/drivers/pwm/sunxi_pwm.c b/drivers/pwm/sunxi_pwm.c
index 8a55e4f461..154a5290ce 100644
--- a/drivers/pwm/sunxi_pwm.c
+++ b/drivers/pwm/sunxi_pwm.c
@@ -47,6 +47,9 @@ static int sunxi_pwm_config_pinmux(void)
 {
 #ifdef CONFIG_MACH_SUN50I
 	sunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM);
+#endif
+#if defined(CONFIG_MACH_SUN8I_V3S) || defined(CONFIG_MACH_SUN8I_S3)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(4), SUN4I_GPB_PWM);
 #endif
 	return 0;
 }
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index f678aa4826..2574a6fd4b 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -1875,6 +1875,7 @@ allocate_instance(struct device *dev,
 
 	musb->controller = dev;
 
+	musb->dyn_fifo = config->dyn_fifo;
 	return musb;
 }
 
diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c
index 8333ddc44c..13be7a11e0 100644
--- a/drivers/video/sunxi/sunxi_de2.c
+++ b/drivers/video/sunxi/sunxi_de2.c
@@ -23,12 +23,21 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_MACH_SUN8I_V3S) || defined(CONFIG_MACH_SUN8I_S3)
+enum {
+	/* Maximum LCD size we support */
+	LCD_MAX_WIDTH		= 1024,
+	LCD_MAX_HEIGHT		= 768,
+	LCD_MAX_LOG2_BPP	= VIDEO_BPP32,
+};
+#else
 enum {
 	/* Maximum LCD size we support */
 	LCD_MAX_WIDTH		= 3840,
 	LCD_MAX_HEIGHT		= 2160,
 	LCD_MAX_LOG2_BPP	= VIDEO_BPP32,
 };
+#endif
 
 static void sunxi_de2_composer_init(void)
 {
@@ -43,13 +52,19 @@ static void sunxi_de2_composer_init(void)
 	reg_value &= ~(0x01 << 24);
 	writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
 #endif
-
+#if defined(CONFIG_MACH_SUN8I_V3S) || defined(CONFIG_MACH_SUN8I_S3)
+	unsigned int hz = 300000000;
+	int pll = clock_get_pll6() * 2;
+	int div = 1;
+	while ((pll / div) > hz)
+		div++;
+	writel(CCM_DE2_CTRL_GATE | CCM_DE2_CTRL_PLL6_2X | CCM_DE2_CTRL_M(div), &ccm->de_clk_cfg);
+#else
 	clock_set_pll10(432000000);
-
 	/* Set DE parent to pll10 */
 	clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK,
 			CCM_DE2_CTRL_PLL10);
-
+#endif
 	/* Set ahb gating to pass */
 	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE);
 	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE);
@@ -74,14 +89,13 @@ static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,
 	struct de_ui * const de_ui_regs =
 		(struct de_ui *)(de_mux_base +
 				 SUNXI_DE2_MUX_CHAN_REGS +
-				 SUNXI_DE2_MUX_CHAN_SZ * 1);
+				 SUNXI_DE2_MUX_CHAN_SZ * SUNXI_DE2_MUX_CHAN_SZ_COUNT);
 	struct de_csc * const de_csc_regs =
 		(struct de_csc *)(de_mux_base +
 				  SUNXI_DE2_MUX_DCSC_REGS);
 	u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ);
 	int channel;
 	u32 format;
-
 	/* enable clock */
 #ifdef CONFIG_MACH_SUN8I_H3
 	setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4);
@@ -108,13 +122,12 @@ static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,
 
 	writel(0x00000101, &de_bld_regs->fcolor_ctl);
 
-	writel(1, &de_bld_regs->route);
+	writel(SUNXI_DE2_BLD_ROUTE, &de_bld_regs->route);
 
 	writel(0, &de_bld_regs->premultiply);
 	writel(0xff000000, &de_bld_regs->bkcolor);
 
 	writel(0x03010301, &de_bld_regs->bld_mode[0]);
-
 	writel(size, &de_bld_regs->output_size);
 	writel(mode->flags & DISPLAY_FLAGS_INTERLACED ? 2 : 0,
 	       &de_bld_regs->out_ctl);
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
index c87c919a52..949b41732e 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -395,6 +395,8 @@ U_BOOT_DRIVER(sunxi_dw_hdmi) = {
 	.priv_auto_alloc_size = sizeof(struct sunxi_dw_hdmi_priv),
 };
 
+#if !defined(CONFIG_MACH_SUN8I_V3S) && !defined(CONFIG_MACH_SUN8I_S3)
 U_BOOT_DEVICE(sunxi_dw_hdmi) = {
 	.name = "sunxi_dw_hdmi"
 };
+#endif
diff --git a/drivers/video/sunxi/sunxi_lcd.c b/drivers/video/sunxi/sunxi_lcd.c
index 619f5892f5..bc0a782a1c 100644
--- a/drivers/video/sunxi/sunxi_lcd.c
+++ b/drivers/video/sunxi/sunxi_lcd.c
@@ -24,7 +24,7 @@ struct sunxi_lcd_priv {
 
 static void sunxi_lcdc_config_pinmux(void)
 {
-#ifdef CONFIG_MACH_SUN50I
+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I_V3S) || defined(CONFIG_MACH_SUN8I_S3)
 	int pin;
 
 	for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(21); pin++) {
@@ -144,7 +144,7 @@ U_BOOT_DRIVER(sunxi_lcd) = {
 	.priv_auto_alloc_size = sizeof(struct sunxi_lcd_priv),
 };
 
-#ifdef CONFIG_MACH_SUN50I
+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I_V3S) || defined(CONFIG_MACH_SUN8I_S3)
 U_BOOT_DEVICE(sunxi_lcd) = {
 	.name = "sunxi_lcd"
 };
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 0ef289fd64..da3080cc32 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -144,12 +144,12 @@
 #define CONFIG_SYS_MMC_MAX_DEVICE	4
 #endif
 
-#ifndef CONFIG_MACH_SUN8I_V3S
-/* 64MB of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (64 << 20))
-#else
+#if defined(CONFIG_MACH_SUN8I_V3S) || defined(CONFIG_MACH_SUN8I_S3)
 /* 2MB of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (2 << 20))
+#else
+/* 64MB of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (64 << 20))
 #endif
 
 /*
@@ -301,19 +301,8 @@ extern int soft_i2c_gpio_scl;
 #define RAMDISK_ADDR_R	__stringify(SDRAM_OFFSET(FE00000))
 
 #else
-/*
- * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc.
- * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
- * 1M script, 1M pxe and the ramdisk at the end.
- */
-#ifndef CONFIG_MACH_SUN8I_V3S
-#define BOOTM_SIZE     __stringify(0xa000000)
-#define KERNEL_ADDR_R  __stringify(SDRAM_OFFSET(2000000))
-#define FDT_ADDR_R     __stringify(SDRAM_OFFSET(3000000))
-#define SCRIPT_ADDR_R  __stringify(SDRAM_OFFSET(3100000))
-#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000))
-#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000))
-#else
+
+#if defined(CONFIG_MACH_SUN8I_V3S) || defined(CONFIG_MACH_SUN8I_S3)
 /*
  * 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc.
  * 16M uncompressed kernel, 8M compressed kernel, 1M fdt,
@@ -325,6 +314,18 @@ extern int soft_i2c_gpio_scl;
 #define SCRIPT_ADDR_R  __stringify(SDRAM_OFFSET(1900000))
 #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(1A00000))
 #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1B00000))
+#else
+/*
+ * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc.
+ * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
+ * 1M script, 1M pxe and the ramdisk at the end.
+ */
+#define BOOTM_SIZE     __stringify(0xa000000)
+#define KERNEL_ADDR_R  __stringify(SDRAM_OFFSET(2000000))
+#define FDT_ADDR_R     __stringify(SDRAM_OFFSET(3000000))
+#define SCRIPT_ADDR_R  __stringify(SDRAM_OFFSET(3100000))
+#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000))
+#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000))
 #endif
 #endif
 
@@ -427,6 +428,14 @@ extern int soft_i2c_gpio_scl;
 
 #include <config_distro_bootcmd.h>
 
+#ifdef CONFIG_CMD_FASTBOOT
+#define FASTBOOT_SETTINGS \
+	"boot_targets=fel mmc_auto usb0 fastboot\0" \
+	"bootcmd_fastboot=fastboot usb 0\0" 
+#else
+#define FASTBOOT_SETTINGS
+#endif
+
 #ifdef CONFIG_USB_KEYBOARD
 #define CONSOLE_STDIN_SETTINGS \
 	"preboot=usb start\0" \
@@ -436,11 +445,25 @@ extern int soft_i2c_gpio_scl;
 	"stdin=serial\0"
 #endif
 
+#ifdef CONFIG_DM_VIDEO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_BMP_16BPP
+#define CONFIG_BMP_24BPP
+#define CONFIG_BMP_32BPP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SOURCE
+#define SPLASHIMAGE_ENV_SETTINGS "splashimage=" __stringify(SDRAM_OFFSET(2000000)) "\0"
+#define CONFIG_ENV_DYNAMIC_DEFAULT
+#else
+#define SPLASHIMAGE_ENV_SETTINGS
+#endif
+
 #ifdef CONFIG_VIDEO
 #define CONSOLE_STDOUT_SETTINGS \
 	"stdout=serial,vga\0" \
 	"stderr=serial,vga\0"
-#elif CONFIG_DM_VIDEO
+#else
+#if CONFIG_DM_VIDEO && !defined(CONFIG_SPLASH_SCREEN)
 #define CONSOLE_STDOUT_SETTINGS \
 	"stdout=serial,vidconsole\0" \
 	"stderr=serial,vidconsole\0"
@@ -449,6 +472,7 @@ extern int soft_i2c_gpio_scl;
 	"stdout=serial\0" \
 	"stderr=serial\0"
 #endif
+#endif
 
 #ifdef CONFIG_MTDIDS_DEFAULT
 #define SUNXI_MTDIDS_DEFAULT \
@@ -464,11 +488,18 @@ extern int soft_i2c_gpio_scl;
 #define SUNXI_MTDPARTS_DEFAULT
 #endif
 
+#if defined(CONFIG_MACH_SUN8I_V3S) || defined(CONFIG_MACH_SUN8I_S3)
+#define PARTS_DEFAULT \
+	"name=loader,start=8k,size=1024k;" \
+	"name=esp,size=16M,bootable,uuid=${uuid_gpt_esp};" \
+	"name=system,size=-,uuid=${uuid_gpt_system};"
+#else
 #define PARTS_DEFAULT \
 	"name=loader1,start=8k,size=32k,uuid=${uuid_gpt_loader1};" \
 	"name=loader2,size=984k,uuid=${uuid_gpt_loader2};" \
 	"name=esp,size=128M,bootable,uuid=${uuid_gpt_esp};" \
 	"name=system,size=-,uuid=${uuid_gpt_system};"
+#endif
 
 #define UUID_GPT_ESP "c12a7328-f81f-11d2-ba4b-00a0c93ec93b"
 
@@ -490,6 +521,7 @@ extern int soft_i2c_gpio_scl;
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	CONSOLE_ENV_SETTINGS \
+	SPLASHIMAGE_ENV_SETTINGS \
 	MEM_LAYOUT_ENV_SETTINGS \
 	DFU_ALT_INFO_RAM \
 	"fdtfile=" FDTFILE "\0" \
@@ -500,10 +532,12 @@ extern int soft_i2c_gpio_scl;
 	"uuid_gpt_system=" UUID_GPT_SYSTEM "\0" \
 	"partitions=" PARTS_DEFAULT "\0" \
 	BOOTCMD_SUNXI_COMPAT \
-	BOOTENV
+	BOOTENV \
+	FASTBOOT_SETTINGS
 
 #else /* ifndef CONFIG_SPL_BUILD */
 #define CONFIG_EXTRA_ENV_SETTINGS
 #endif
 
 #endif /* _SUNXI_COMMON_CONFIG_H */
+
diff --git a/include/init.h b/include/init.h
index 2a33a3fd1e..95bb92f51c 100644
--- a/include/init.h
+++ b/include/init.h
@@ -203,6 +203,7 @@ int update_flash_size(int flash_size);
 int arch_early_init_r(void);
 void pci_init(void);
 int misc_init_r(void);
+int initr_env_dynamic_default(void);
 #if defined(CONFIG_VID)
 int init_func_vid(void);
 #endif
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 6908431d03..b3414bb3a0 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -426,6 +426,7 @@ CONFIG_ENV_ADDR_FLEX
 CONFIG_ENV_CALLBACK_LIST_DEFAULT
 CONFIG_ENV_CALLBACK_LIST_STATIC
 CONFIG_ENV_COMMON_BOOT
+CONFIG_ENV_DYNAMIC_DEFAULT
 CONFIG_ENV_EEPROM_IS_ON_I2C
 CONFIG_ENV_FLAGS_LIST_DEFAULT
 CONFIG_ENV_FLAGS_LIST_STATIC

[   85.238760] usb 1-1.4: new high-speed USB device number 35 using ehci-platform
[   85.418843] usb 1-1.4: New USB device found, idVendor=148f, idProduct=7601, bcdDevice= 0.00
[   85.427206] usb 1-1.4: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[   85.434540] usb 1-1.4: Product: 802.11 n WLAN
[   85.438909] usb 1-1.4: SerialNumber: 1.0
[   85.658773] usb 1-1.4: reset high-speed USB device number 35 using ehci-platform
[   85.711960] mt7601u 1-1.4:1.0: ASIC revision: 76010001 MAC revision: 76010500
[   85.720941] mt7601u 1-1.4:1.0: Firmware Version: 0.1.00 Build: 7640 Build time: 201302052146____
[   86.167971] mt7601u 1-1.4:1.0: EEPROM ver:0c fae:00
[   86.366367] mt7601u 1-1.4:1.0: rx urb failed: -71
[   86.371220] mt7601u 1-1.4:1.0: Error: MCU resp urb failed:-71
[   86.376970] mt7601u 1-1.4:1.0: Error: MCU resp evt:0 seq:5-4!
[   86.386490] mt7601u 1-1.4:1.0: rx urb failed: -71
[   86.391620] mt7601u 1-1.4:1.0: Error: MCU resp urb failed:-71
[   86.397381] mt7601u 1-1.4:1.0: Error: MCU resp evt:0 seq:5-4!
[   86.406739] mt7601u 1-1.4:1.0: rx urb failed: -71
[   86.411822] mt7601u 1-1.4:1.0: Error: MCU resp urb failed:-71
[   86.417575] mt7601u 1-1.4:1.0: Error: MCU resp evt:0 seq:5-4!
[   86.426855] mt7601u 1-1.4:1.0: rx urb failed: -71
[   86.431907] mt7601u 1-1.4:1.0: Error: MCU resp urb failed:-71
[   86.437675] mt7601u 1-1.4:1.0: Error: MCU resp evt:0 seq:5-4!
[   86.446980] mt7601u 1-1.4:1.0: rx urb failed: -71
[   86.452029] mt7601u 1-1.4:1.0: Error: MCU resp urb failed:-71
[   86.457789] mt7601u 1-1.4:1.0: Error: MCU resp evt:0 seq:5-4!
[   86.463589] mt7601u 1-1.4:1.0: Error: mt7601u_mcu_wait_resp timed out
[   86.778760] mt7601u 1-1.4:1.0: Vendor request req:07 off:0080 failed:-71
[   87.088761] mt7601u 1-1.4:1.0: Vendor request req:02 off:0080 failed:-71
[   87.398756] mt7601u 1-1.4:1.0: Vendor request req:02 off:0080 failed:-71
[   87.405586] mt7601u: probe of 1-1.4:1.0 failed with error -110
[   87.420875] usb 1-1.4: USB disconnect, device number 35

mkimage -C none -A arm -T script -d boot.cmd boot.scr

/*
 * Allwinner A20/A31 SoCs NMI IRQ chip driver.
 *
 * Carlo Caione <carlo.caione@gmail.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#define DRV_NAME	"sunxi-nmi"
#define pr_fmt(fmt)	DRV_NAME ": " fmt

#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>

#define SUNXI_NMI_SRC_TYPE_MASK	0x00000003

#define SUNXI_NMI_IRQ_BIT	BIT(0)

#define SUN6I_R_INTC_CTRL	0x0c
#define SUN6I_R_INTC_PENDING	0x10
#define SUN6I_R_INTC_ENABLE	0x40

/*
 * For deprecated sun6i-a31-sc-nmi compatible.
 * Registers are offset by 0x0c.
 */
#define SUN6I_R_INTC_NMI_OFFSET	0x0c
#define SUN6I_NMI_CTRL		(SUN6I_R_INTC_CTRL - SUN6I_R_INTC_NMI_OFFSET)
#define SUN6I_NMI_PENDING	(SUN6I_R_INTC_PENDING - SUN6I_R_INTC_NMI_OFFSET)
#define SUN6I_NMI_ENABLE	(SUN6I_R_INTC_ENABLE - SUN6I_R_INTC_NMI_OFFSET)

#define SUN7I_NMI_CTRL		0x00
#define SUN7I_NMI_PENDING	0x04
#define SUN7I_NMI_ENABLE	0x08

#define SUN9I_NMI_CTRL		0x00
#define SUN9I_NMI_ENABLE	0x04
#define SUN9I_NMI_PENDING	0x08

#define SUN8I_NMI_CTRL		0xd0
#define SUN8I_NMI_ENABLE	0xd4
#define SUN8I_NMI_PENDING	0xd8

enum {
	SUNXI_SRC_TYPE_LEVEL_LOW = 0,
	SUNXI_SRC_TYPE_EDGE_FALLING,
	SUNXI_SRC_TYPE_LEVEL_HIGH,
	SUNXI_SRC_TYPE_EDGE_RISING,
};

struct sunxi_sc_nmi_reg_offs {
	u32 ctrl;
	u32 pend;
	u32 enable;
};

static const struct sunxi_sc_nmi_reg_offs sun6i_r_intc_reg_offs __initconst = {
	.ctrl	= SUN6I_R_INTC_CTRL,
	.pend	= SUN6I_R_INTC_PENDING,
	.enable	= SUN6I_R_INTC_ENABLE,
};

static const struct sunxi_sc_nmi_reg_offs sun6i_reg_offs __initconst = {
	.ctrl	= SUN6I_NMI_CTRL,
	.pend	= SUN6I_NMI_PENDING,
	.enable	= SUN6I_NMI_ENABLE,
};

static const struct sunxi_sc_nmi_reg_offs sun7i_reg_offs __initconst = {
	.ctrl	= SUN7I_NMI_CTRL,
	.pend	= SUN7I_NMI_PENDING,
	.enable	= SUN7I_NMI_ENABLE,
};

static const struct sunxi_sc_nmi_reg_offs sun9i_reg_offs __initconst = {
	.ctrl	= SUN9I_NMI_CTRL,
	.pend	= SUN9I_NMI_PENDING,
	.enable	= SUN9I_NMI_ENABLE,
};

static const struct sunxi_sc_nmi_reg_offs sun8i_reg_offs __initconst = {
	.ctrl	= SUN8I_NMI_CTRL,
	.pend	= SUN8I_NMI_PENDING,
	.enable	= SUN8I_NMI_ENABLE,
};

static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off,
				      u32 val)
{
	irq_reg_writel(gc, val, off);
}

static inline u32 sunxi_sc_nmi_read(struct irq_chip_generic *gc, u32 off)
{
	return irq_reg_readl(gc, off);
}

static void sunxi_sc_nmi_handle_irq(struct irq_desc *desc)
{
	struct irq_domain *domain = irq_desc_get_handler_data(desc);
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int virq = irq_find_mapping(domain, 0);

	chained_irq_enter(chip, desc);
	generic_handle_irq(virq);
	chained_irq_exit(chip, desc);
}

static int sunxi_sc_nmi_set_type(struct irq_data *data, unsigned int flow_type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
	struct irq_chip_type *ct = gc->chip_types;
	u32 src_type_reg;
	u32 ctrl_off = ct->regs.type;
	unsigned int src_type;
	unsigned int i;

	irq_gc_lock(gc);

	switch (flow_type & IRQF_TRIGGER_MASK) {
	case IRQ_TYPE_EDGE_FALLING:
		src_type = SUNXI_SRC_TYPE_EDGE_FALLING;
		break;
	case IRQ_TYPE_EDGE_RISING:
		src_type = SUNXI_SRC_TYPE_EDGE_RISING;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		src_type = SUNXI_SRC_TYPE_LEVEL_HIGH;
		break;
	case IRQ_TYPE_NONE:
	case IRQ_TYPE_LEVEL_LOW:
		src_type = SUNXI_SRC_TYPE_LEVEL_LOW;
		break;
	default:
		irq_gc_unlock(gc);
		pr_err("Cannot assign multiple trigger modes to IRQ %d.\n",
			data->irq);
		return -EBADR;
	}

	irqd_set_trigger_type(data, flow_type);
	irq_setup_alt_chip(data, flow_type);

	for (i = 0; i < gc->num_ct; i++, ct++)
		if (ct->type & flow_type)
			ctrl_off = ct->regs.type;

	src_type_reg = sunxi_sc_nmi_read(gc, ctrl_off);
	src_type_reg &= ~SUNXI_NMI_SRC_TYPE_MASK;
	src_type_reg |= src_type;
	sunxi_sc_nmi_write(gc, ctrl_off, src_type_reg);

	irq_gc_unlock(gc);

	return IRQ_SET_MASK_OK;
}

static int __init sunxi_sc_nmi_irq_init(struct device_node *node,
					const struct sunxi_sc_nmi_reg_offs *reg_offs)
{
	struct irq_domain *domain;
	struct irq_chip_generic *gc;
	unsigned int irq;
	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
	int ret;


	domain = irq_domain_add_linear(node, 1, &irq_generic_chip_ops, NULL);
	if (!domain) {
		pr_err("Could not register interrupt domain.\n");
		return -ENOMEM;
	}

	ret = irq_alloc_domain_generic_chips(domain, 1, 2, DRV_NAME,
					     handle_fasteoi_irq, clr, 0,
					     IRQ_GC_INIT_MASK_CACHE);
	if (ret) {
		pr_err("Could not allocate generic interrupt chip.\n");
		goto fail_irqd_remove;
	}

	irq = irq_of_parse_and_map(node, 0);
	if (irq <= 0) {
		pr_err("unable to parse irq\n");
		ret = -EINVAL;
		goto fail_irqd_remove;
	}

	gc = irq_get_domain_generic_chip(domain, 0);
	gc->reg_base = of_io_request_and_map(node, 0, of_node_full_name(node));
	if (IS_ERR(gc->reg_base)) {
		pr_err("unable to map resource\n");
		ret = PTR_ERR(gc->reg_base);
		goto fail_irqd_remove;
	}

	gc->chip_types[0].type			= IRQ_TYPE_LEVEL_MASK;
	gc->chip_types[0].chip.irq_mask		= irq_gc_mask_clr_bit;
	gc->chip_types[0].chip.irq_unmask	= irq_gc_mask_set_bit;
	gc->chip_types[0].chip.irq_eoi		= irq_gc_ack_set_bit;
	gc->chip_types[0].chip.irq_set_type	= sunxi_sc_nmi_set_type;
	gc->chip_types[0].chip.flags		= IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED;
	gc->chip_types[0].regs.ack		= reg_offs->pend;
	gc->chip_types[0].regs.mask		= reg_offs->enable;
	gc->chip_types[0].regs.type		= reg_offs->ctrl;

	gc->chip_types[1].type			= IRQ_TYPE_EDGE_BOTH;
	gc->chip_types[1].chip.name		= gc->chip_types[0].chip.name;
	gc->chip_types[1].chip.irq_ack		= irq_gc_ack_set_bit;
	gc->chip_types[1].chip.irq_mask		= irq_gc_mask_clr_bit;
	gc->chip_types[1].chip.irq_unmask	= irq_gc_mask_set_bit;
	gc->chip_types[1].chip.irq_set_type	= sunxi_sc_nmi_set_type;
	gc->chip_types[1].regs.ack		= reg_offs->pend;
	gc->chip_types[1].regs.mask		= reg_offs->enable;
	gc->chip_types[1].regs.type		= reg_offs->ctrl;
	gc->chip_types[1].handler		= handle_edge_irq;

	/* Disable any active interrupts */
	sunxi_sc_nmi_write(gc, reg_offs->enable, 0);

	/* Clear any pending NMI interrupts */
	sunxi_sc_nmi_write(gc, reg_offs->pend, SUNXI_NMI_IRQ_BIT);

	irq_set_chained_handler_and_data(irq, sunxi_sc_nmi_handle_irq, domain);

	return 0;

fail_irqd_remove:
	irq_domain_remove(domain);

	return ret;
}

static int __init sun6i_r_intc_irq_init(struct device_node *node,
					struct device_node *parent)
{
	return sunxi_sc_nmi_irq_init(node, &sun6i_r_intc_reg_offs);
}
IRQCHIP_DECLARE(sun6i_r_intc, "allwinner,sun6i-a31-r-intc",
		sun6i_r_intc_irq_init);

static int __init sun6i_sc_nmi_irq_init(struct device_node *node,
					struct device_node *parent)
{
	return sunxi_sc_nmi_irq_init(node, &sun6i_reg_offs);
}
IRQCHIP_DECLARE(sun6i_sc_nmi, "allwinner,sun6i-a31-sc-nmi", sun6i_sc_nmi_irq_init);

static int __init sun7i_sc_nmi_irq_init(struct device_node *node,
					struct device_node *parent)
{
	return sunxi_sc_nmi_irq_init(node, &sun7i_reg_offs);
}
IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-a20-sc-nmi", sun7i_sc_nmi_irq_init);

static int __init sun9i_nmi_irq_init(struct device_node *node,
				     struct device_node *parent)
{
	return sunxi_sc_nmi_irq_init(node, &sun9i_reg_offs);
}
IRQCHIP_DECLARE(sun9i_nmi, "allwinner,sun9i-a80-nmi", sun9i_nmi_irq_init);

static int __init sun8i_nmi_irq_init(struct device_node *node,
				     struct device_node *parent)
{
	return sunxi_sc_nmi_irq_init(node, &sun8i_reg_offs);
}
IRQCHIP_DECLARE(sun8i_nmi, "allwinner,sun8i-v3s-nmi", sun8i_nmi_irq_init);

        nmi_intc: interrupt-controller@01c00000 {
            compatible = "allwinner,sun8i-v3s-nmi";
            interrupt-controller;
            #interrupt-cells = <2>;
            reg = <0x01c00000 0x400>;
            interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
        };

/ {
        nmi_intc: interrupt-controller@1c000d0 {
            compatible = "allwinner,sun6i-a31-r-intc";
            interrupt-controller;
            #interrupt-cells = <2>;
            reg = <0x01c000d0 0x400>;
            interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
        };
};
&i2c0 {
    status = "okay";
    axp209: pmic@34 {
        reg = <0x34>;
        interrupt-parent = <&nmi_intc>;
        interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
    };
};

#include "axp209.dtsi"

&usb_power_supply {
    status = "okay";
};

&ac_power_supply {
    status = "okay";
};

&battery_power_supply {
    status = "okay";
};

&reg_dcdc2 {
    regulator-always-on;
    regulator-min-microvolt = <1250000>;
    regulator-max-microvolt = <1250000>;
    regulator-name = "vdd-cpu";
};

&reg_dcdc3 {
    regulator-always-on;
    regulator-min-microvolt = <3300000>;
    regulator-max-microvolt = <3300000>;
    regulator-name = "vdd-device";
};

&reg_ldo1 {
    regulator-min-microvolt = <3300000>;
    regulator-max-microvolt = <3300000>;
    regulator-name = "vdd-rtc";
};

&reg_ldo2 {
    regulator-always-on;
    regulator-min-microvolt = <3000000>;
    regulator-max-microvolt = <3000000>;
    regulator-name = "avcc";
};